LEAKAGE POWER REDUCTION IN CMOS CIRCUITS USING LEAKAGE CONTROL TRANSISTOR TECHNIQUE IN NANOSCALE TECHNOLOGY
نویسندگان
چکیده
منابع مشابه
Leakage Power Reduction in Cmos Circuits Using Leakage Control Transistor Technique in Nanoscale Technology
In CMOS circuits, as the technology scales down to nanoscale, the sub-threshold leakage current increases with the decrease in the threshold voltage. LECTOR, a technique to tackle the leakage problem in CMOS circuits, uses two additional leakage control transistors, which are self-controlled, in a path from supply to ground which provides the additional resistance thereby reducing the leakage c...
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ژورنال
عنوان ژورنال: International Journal of Electronics Signals and Systems
سال: 2013
ISSN: 2231-5969
DOI: 10.47893/ijess.2013.1113