Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment
نویسندگان
چکیده
In nano-scale CMOS technology, circuit reliability is a growing concern for complicated digital circuits due to manufacturing process variation and aging effects. this paper, statistical optimization framework presented analyze improve the lifetime of in presence degradation. The proposed takes advantage variation- aging-aware gate-level delay degradation model characterize evaluate combinational circuits. A metric called Guardband-Aware Reliability (abbreviated as GAR) fair evaluation considering guardband timing yield specified by designer. Then, using criticality metric, set statistically critical gates selected being optimized framework. As improvement procedure, dual-threshold voltage assignment technique applied identified enable manufactured chip terms low loss. Experimental results on ISCAS'85 ISCAS'89 benchmark show that our increases up 9.93% 6-year imposing less than 6.9%
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ژورنال
عنوان ژورنال: IEEE Access
سال: 2021
ISSN: ['2169-3536']
DOI: https://doi.org/10.1109/access.2021.3103200