Macro Model for Discrete-Time Sigma‒Delta Modulators
نویسندگان
چکیده
This work presents a macro model for discrete-time sigma‒delta modulators, which can significantly reduce the simulation time compared to transistor level circuits. The proposed is realized by effectively combining active and passive ideal circuit components with Verilog-A modules. As such, since true representation of actual circuit, moderately good accuracy be obtained. In addition, includes major amplifier, comparator, switch‒capacitor non-idealities modulator such as amplifier DC gain, GBW, slewrate, comparator bandwidth, hysteresis, parasitic capacitance, switch-on resistance. results show only 6.43% comparable accuracy. result, facilitate design leverage non-ideality analysis modulators. practical example, second order five-level quantizer using propose GSM WCDMA applications.
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ژورنال
عنوان ژورنال: Electronics
سال: 2022
ISSN: ['2079-9292']
DOI: https://doi.org/10.3390/electronics11233994