On the Critical Role of Ferroelectric Thickness for Negative Capacitance Device-Circuit Interaction

This paper demonstrates the critical role that Ferroelectric (FE) layer thickness (tFE) plays in Negative Capacitance (NC) transistors connecting device and circuit levels together. The study is done through fully-calibrated TCAD simulations for a 14nm FDSOI technology node, exploring impact of tFE on figures merit n-type p-type devices, voltage transfer characteristic (VTC) noise margin inverter as well speed buffer circuits. First, we analyze electrical parameters (e.g., ION, SS, ION/IOFF Cgg) by varying up to maximum level at which hysteresis I-V starts. Then, deleterious Differential Resistance (NDR), due drain gate coupling, demonstrating how it imposes an additional constraint limiting tFE. We show consequences NDR effects VTC inverter, are essential components constructing robust clock trees any chip. demonstrate considerable increase gate’s capacitance FE seriously degrades circuit’s performance imposing further constraints Further, SRAM cell static metrics such hold (HNM), read (RNM) write (WNM) supply voltages 0.7V 0.4V. HNM RNM NC-FDSOI FET based higher then those baseline with However, WNM general follows non monotonic trend w.r.t tFE, also depends voltage. Finally, optimize design considering overall metrics. All all, our analysis provides guidance designers select optimal NCFETs hysteresis-free operations, reliability, optimized.