Programming parallel dense matrix factorizations and inversion for new-generation NUMA architectures

We propose a methodology to address the programmability issues derived from emergence of new-generation shared-memory NUMA architectures. For this purpose, we employ dense matrix factorizations and inversion (DMFI) as use case, target two modern architectures (AMD Rome Huawei Kunpeng 920) that exhibit configurable topologies. Our pursues performance portability across different configurations by proposing multi-domain implementations for DMFI plus hybrid task- loop-level parallelization configures multi-threaded executions fix core-to-data binding, exploiting locality at expense minor code modifications. In addition, introduce generalization offers support virtually any topology in present future experimentation on three representative linear algebra operations validates proposal, reveals insights necessity adapting both codes their execution improve data access locality, reports inter- intra-socket competitive with state-of-the-art message-passing implementations, maintaining ease development usually associated programming.