Sampling circuit issues in A/D converters and challenges for the solution

This paper discusses issues of sampling circuits in analog-to-digital converter (ADC) and reviews some papers describing challenges for the solution to this fundamental issue ADC. The energy consumption ADC is essentially determined by capacitance. peak current input signal circuit about 10 times larger than that continuous-time (CT) increases with resolution conversion frequency. A CT-pipelined using an analog delay has been proposed address issue. Noise considered unavoidable large capacitance be required suppress noise, but it shown noise can suppressed placing amplifier front changing position timing.