Scalable Network-on-Chip Architectures for Brain–Machine Interface Applications
نویسندگان
چکیده
منابع مشابه
Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)
Nowadays, faults and failures are increasing especially in complex systems such as Network-on-Chip (NoC) based Systems-on-a-Chip due to the increasing susceptibility and decreasing feature sizes. On the other hand, fault-tolerant routing algorithms have an evident effect on tolerating permanent faults and improving the reliability of a Network-on-Chip based system. This paper presents reliabili...
متن کاملHigh-Performance, Scalable Optical Network-On-Chip Architectures
..................................................................................................................... III TABLE OF CONTENTS ................................................................................................... V LIST OF TABLES ........................................................................................................... VII LIST OF FIGURES ...............
متن کاملA Scalable and Adaptive Network on Chip for Many-Core Architectures
The continuous observance of Moore’s law has enabled to continuously implement increasingly powerful single-core processors than in the past. The increase of clock frequency and complexity of the microarchitecture were previously the main means enabling this performance enhancement. However, physical and architectural limitations necessitated a rethinking in recent times. Instead of increasing ...
متن کاملZooming in on Network-on-Chip Architectures
The aim of this paper is to expose the networking community to the concept of network-on-chip (NoC), an emerging field of study within the VLSI realm, in which networking principles play a significant role, and new network architectures are in demand. Networking researchers will find new challenges in exploring solutions to familiar problems such as network design, routing, and quality-of-servi...
متن کاملEfficient On-Chip Pipelined Streaming Computations on Scalable Manycore Architectures
Performance of manycore processors is limited by programs’ use of off-chip main memory. Streaming computation organized in a pipeline limits accesses to main memory to tasks at boundaries of the pipeline to read or write to main memory. The Single Chip Cloud computer (SCC) offers 48 cores linked by a highspeed on-chip network, and allows the implementation of such on-chip pipelined technique. W...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
سال: 2018
ISSN: 1063-8210,1557-9999
DOI: 10.1109/tvlsi.2018.2843282