<scp>Tailor</scp> : Altering Skip Connections for Resource-Efficient Inference

Deep neural networks use skip connections to improve training convergence. However, these are costly in hardware, requiring extra buffers and increasing on- off-chip memory utilization bandwidth requirements. In this paper, we show that can be optimized for hardware when tackled with a hardware-software codesign approach. We argue while network’s needed the network learn, they later removed or shortened provide more efficient implementation minimal no accuracy loss. introduce Tailor , tool whose hardware-aware algorithm gradually removes shortens fully trained lower their cost. improves resource by up 34% BRAMs, 13% FFs, 16% LUTs on-chip, dataflow-style architectures. increases performance 30% reduces 45% 2D processing element array architecture.