Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems

Memory Systems: Cache, DRAM, Disk

Operating System Support for NVM+DRAM Hybrid Main Memory

© Operating System Support for NVM+DRAM Hybrid Main Memory Jeffrey C. Mogul, Eduardo Argollo, Mehul Shah, Paolo Faraboschi

Privacy Protection Cache Policy on Hybrid Main Memory

We firstly suggest privacy protection cache policy applying the duty to delete personal information on a hybrid main memory system. This cache policy includes generating random data and overwriting the random data into the personal information. Proposed cache policy is more economical and effective regarding perfect deletion of data.

Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs

This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called \dynamically variable line-size cache (D-VLS cache)". The D-VLS cache can optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth. In our evaluation, it is observed that the performance improvement...

Understanding and Improving the Latency of DRAM-Based Memory Systems

Over the past two decades, the storage capacity and access bandwidth of main memory have improved tremendously, by 128x and 20x, respectively. These improvements are mainly due to the continuous technology scaling of DRAM (dynamic random-access memory), which has been used as the physical substrate for main memory. In stark contrast with capacity and bandwidth, DRAM latency has remained almost ...