Space Optimized Multiplier Architecture for Embedded Cryptoprocessor

Space Optimized Multiplier Architecture for Embedded Cryptoprocessor

The finite field modular multiplier is the most critical component in the elliptic curve crypto processor (ECCP) consuming the maximum chip area and contributing the most to the device latency. Modular multiplication, point multiplication, point doubling are few of the critical activities to be carried out by multiplier in ECC algorithm, and should be managed without compromising on security an...

Optimized Reversible Multiplier Circuit

Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4× 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generaliz...

High performance elliptic curve GF(2k) cryptoprocessor architecture for multimedia

A High Speed, Optimized Multiplier Architecture for a DF-ECC Processor

This paper presents a High speed, optimized multiplier architecture for a dual-field (DF) processor for elliptic curve cryptography (ECC). This processor can support the required operations in both galois prime field GF(p) and binary field GF(2). The performance of the processor is enhanced by the judicious selection of proper type of coordinates in the arithmetic unit. The arithmetic unit is d...

Optimized Architecture of Low Power, High Performance Multiplier for Crypto Chips

The paper presents unified Architecture of an efficient and Low Power Multiplier that can support multiplication based on Galois Fields GF (2). Cryptography Algorithms involve extensive multiplication for encryption and decryption of data using Diffe-Hellman (DH) Key exchange protocol, RSA and Elliptical Curves cryptography. These can be effectively achieved by hardware implementation with very...