Statistical Timing Yield Optimization by Gate Sizing

نویسندگان
چکیده

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Statistical Timing-Yield Optimization via Latch Substitution∗

The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern circuit designs may suffer from uncertain delays, not predictable in the design phase or even after manufacturing. This paper presents an optimization technique to make sequential circuits robust against delay variations and thus ...

متن کامل

Evaluating the Effectiveness of Statistical Gate Sizing for Power Optimization

We evaluate the effectiveness of statistical gate sizing to minimize circuit power. We develop reliable posynomial models for delay and power that are accurate to within 5-10% of 130nm library data. We formulate statistical sizing as a geometric program, accounting for randomness in gate delays. For various ISCAS-85 circuits, statistical sizing at a 99.8% target yield provides 25% power reducti...

متن کامل

Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing

Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep submicrometer integrated circuits. Currently existing algorithms do not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but also simultaneous switching behavior for noise optimization. Based on Lagrangia...

متن کامل

A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis

This paper discusses a gate resizing method for performance enhancement based on statistical static timing analysis. The proposed method focuses on timing uncertainties caused by local random fluctuation. Our method aims to remove both over-design and under-design of a circuit, and realize highperformance and high-reliability LSI design. The effectiveness of our method is examined by 6 benchmar...

متن کامل

Timing Driven Gate Duplication for Delay Optimization

In the past few years gate duplication has been studied as a strategy for cutset minimization in partitioning problems .This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary in-puts(PI) in topologically sorted order evaluating tuples at the input pins...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

سال: 2006

ISSN: 1063-8210

DOI: 10.1109/tvlsi.2006.884166