The design of optimal planar systolic arrays for matrix multiplication

FPGA Implementation of Optimal Planar Systolic Arrays for Orthogonal Matrix Multiplication

In this paper, optimal 2-D Systolic Arrays for orthogonal matrix multiplication, as much as the corresponding hardware implementation is investigated. The selected platform is a FPGA (Field Programmable Gate Array) device since, in systolic computing, FPGAs can be used as dedicated computers in order to perform certain computations at very high frequencies. The description language used as an e...

Reducing the Number of Processors Elements in Systolic Arrays for Matrix Multiplication using Linear Transformation Matrix

Abstract: Besides different definitions, in this work is given the so called transformation matrix, which maps the given index space in another index space. Transformation used in this new index space reduces the number of processing elements in the array. We illustrate all possible instances of transformation matrices and we show the importance of using the transformation matrix by comparing t...

Hyper-Systolic Matrix Multiplication

A novel parallel algorithm for matrix multiplication is presented. The hyper-systolic algorithm makes use of a one-dimensional processor abstraction. The procedure can be implemented on all types of parallel systems. It can handle matrix-vector multiplications as well as transposed matrix products.

Systolic arrays for matrix multiplications

Reducing the Number of Processors Elements in Systolic Arrays for Matrix Multiplication

Author is discussing a problems of determining parameters suitable systolic arrays for implementation regular 3-nested loop algorithms. Author shows that if the characteristics of so called adaptable algorithms to the projection direction are used we have the best results. This characteristics can be space (number of processor elements,chip area, input-output elements, ...), time(flow period of...