Time-Multiplexed In-Memory Computation Scheme for Mapping Quantized Neural Networks on Hybrid CMOS-OxRAM Building Blocks

In this work, we experimentally demonstrate two key building blocks for realizing Binary/Ternary Neural Networks (BNNs/TNNs): (i) 130 nm CMOS based sigmoidal neurons and (ii) HfO$_{2}$ multi-level (MLC) OxRAM-synaptic blocks. An optimized vector matrix multiplication (VMM) programming scheme that utilizes the is also presented. Compared to prior approaches utilize differential synaptic structures, a single device per synapse with sets of READ operations used. Proposed hardware mapping strategy shows performance change $< $5% (decrease 2-5% TNN, increase 0.2% BNN) compared software-based implementation significant memory savings in order 16-32× classification problem on Fashion MNIST (FMNIST) dataset. Impact OxRAM variability Hardware BNN/TNN analyzed.