Time-multiplexed test access architecture for stacked integrated circuits
نویسندگان
چکیده
منابع مشابه
Test-Architecture Optimization for 3D Stacked ICs
TSV-based 3D-SICs significantly impact core-based systemon-chip (SOC) design. Testing of core-based dies in 3D-SICs introduces new challenges [1], [2]. In order to test the dies in a stack, the embedded cores, and the TSVs, a test access mechanism (TAM) must be included on the die to transport test data to the cores, and a 3D TAM is needed to transfer test data to the die from the stack input/o...
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2016
ISSN: 1349-2543
DOI: 10.1587/elex.13.20160314