Timing-Error-Tolerant Network-on-Chip Design Methodology
نویسندگان
چکیده
منابع مشابه
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m × n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of...
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Dit proefschrift is goedgekeurd door de promotor: No parts of this book may be reproduced in any form or by any electronic or mechanical means (including phothocopying, recording, or information storage or retrieval) without prior permission in writing from the author.
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By increasing, the complexity of chips and the need to integrating more components into a chip has made network –on- chip known as an important infrastructure for network communications on the system, and is a good alternative to traditional ways and using the bus. By increasing the density of chips, the possibility of failure in the chip network increases and providing correction and fault tol...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
سال: 2007
ISSN: 0278-0070
DOI: 10.1109/tcad.2007.891371