Toward Efficient Design Space Exploration for Fault-Tolerant Multiprocessor Systems

Fault Tolerant Multiprocessor Systems

Toward Systematic Design of Fault-Tolerant Systems

A s computing and communications become irreplaceable tools of modern society, one fundamental principle emerges: The greater the benefits these systems bring to our well-being and quality of life, the greater the potential for harm when they fail to perform their functions or perform them incorrectly. Consider air, rail, and automobile traffic control; emergency response systems; airline fligh...

Cost-Efficient Fault-Tolerant Router Design for 2D-Mesh Based Chip Multiprocessor Systems

In this paper, a cost-efficient fault-tolerant router design, called 20-Path Router (20PR) architecture, is proposed to reduce the impacts of faulty routers for 2D-mesh based chip multiprocessor systems. The 20PR consists of two fault-tolerant circuits: 1) a Builtin Self-Test and Self-Diagnosis (BIST/SD) circuit to detect and locate faulty FIFOs and MUXs, and 2) a Fault-Isolation (FI) circuit t...

Efficient design space exploration for embedded systems

Design space exploration is an important factor in embedded systems design. During several steps in a state-of-the-art design flow, designers have to decide between many design alternatives. The decisions are located at various levels of abstraction. In addition, the choices affect several design goals, the alternatives therefore represent a multi-criteria decision problem. Further, the space o...

Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems

In this paper, we present a new methodology to rapidly explore the large design space encountered in hardware/software systems. The proposed methodology is based on a fast and accurate estimation approach. It has been implemented as an extension to a hardware/software codesign flow to enable the exploration of a large number of multiprocessor architecture solutions from the very start of the de...