VLSI Architecture for High Performance 3GPP Interleaver/Deinterleaver for Turbo Codes
نویسندگان
چکیده
منابع مشابه
VLSI architectures for turbo codes
A great interest has been gained in recent years by a new error-correcting code technique, known as “turbo coding,” which has been proven to offer performance closer to the Shannon’s limit than traditional concatenated codes. In this paper, several very large scale integration (VLSI) architectures suitable for turbo decoder implementation are proposed and compared in terms of complexity and per...
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ژورنال
عنوان ژورنال: International Journal of Computers Communications & Control
سال: 2014
ISSN: 1841-9844,1841-9836
DOI: 10.15837/ijccc.2014.2.111