Multi-core architectures: Complexities of performance prediction and the impact of cache topology

The balance metric is a simple approach to estimate the performance of bandwidth-limited loop kernels. However, applying the method to in-cache situations and modern multi-core architectures yields unsatisfactory results. This paper analyzes the influence of cache hierarchy design on performance predictions for bandwidth-limited loop kernels on current mainstream processors. We present a diagnostic model with improved predictive power, correcting the limitations of the simple balance metric. The importance of code execution overhead even in bandwidth-bound situations is emphasized. Finally we analyze the impact of synchronization overhead on multi-threaded performance with a special emphasis on the influence of cache topology. J. Treibig · G. Hager · G. Wellein Regionales Rechenzentrum Erlangen, Friedrich-Alexander Universität Erlangen-Nürnberg, Martensstr. 1, D-91058 Erlangen, Germany e-mail: {jan.treibig,georg.hager,gerhard.wellein}@rrze.uni-erlangen.de 1 ar X iv :0 91 0. 48 65 v1 [ cs .P F] 2 6 O ct 2 00 9