Experimental Studies on Test Pattern Generation for BDD Circuits

Synthesis for Testability has become a major issue as the size and complexity of circuits and systems is rapidly increasing. Due to their good testability design styles based on multiplexors have become very popular. Starting from a function description as a Binary Decision Diagram (BDD) the circuit is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under the Stuck-At Fault Model. In this paper we study Automatic Test Pattern Generation (ATPG) for circuits derived from Binary Decision Diagrams (BDDs) under the Stuck-At fault model. Experimental studies for circuits derived from BDDs in comparison to optimized circuits are carried out. For the benchmark circuits the number of test patterns needed is comparable to the relative sizes of the circuits. Even a gain up to a factor of four occurred