ESTO: A Performance Estimation Approach for Efficient Design Space Exploration
چکیده
Recent advancements in CMOS fabrication and processor architectures have posed new challenges to the chip designers. The availability of a large number of design configurations, along with constraints such as energy consumption and real-time response demand exploring a large design-space for choosing the best possible configuration. However, the high cost of detailed simulators prohibit the designers from doing this. The existing techniques of performance estimation generally use intrusive methods or have high overhead or inaccuracy and hence, are not suitable for real-world processors. In this paper we present ESTO, a simulation-based approach for estimating application performance (execution time and energy) under multiple last level cache (LLC) configurations. ESTO uses a multi-level profiling cache which provides low-cost and non-intrusive dynamic profiling. A unique feature of ESTO is its ability to estimate performance of a cache of higher size than the baseline cache present. Experiments performed using a state-of-art simulator and benchmarks from SPEC2006 suite show the effectiveness of ESTO. For our workload, the average error in estimating execution time and memory subsystem energy are 3.7% and 3.3% respectively.