Inverse Quantization on FPGA-augmented TriMedia

This paper investigates inverse quantization on FPGA-augmented TriMedia processor. First, we outline the extension of TriMedia architecture consisting of FPGAbased Reconfigurable Functional Units (RFU) and associated generic instructions. Then we analyse an IQ-4 (RFU– specific) instruction which can process four coefficients per call, and propose a scheme to implement the IQ-4 operation on the RFU. When mapped on an ACEX EP1K100 FPGA, the proposed IQ-4 exhibits a latency of 18 and a recovery of 2 TriMedia-32@200 MHz cycles, and occupies 43% of the device. By configuring the IQ-4 facility on the RFU at application load-time, inverse quantization can be computed on FPGA-augmented TriMedia with a speed-up of 1:5 over the standard TriMedia. Keywords—Reconfigurable computing; inverse quantization; VLIW processors; field-programmable gate arrays.