A Study of the Influence of the POWER5 Dynamic Resource Balancing (DRB) on Optimal Hardware Thread Priorities

Simultaneous Multithreading, often abbreviated SMT, is a technique for improving the overall efficiency of superscalar processors with hardware multithreading. SMT permits a processor to concurrently execute multiple independent instruction streams every clock cycle, potentially improving processor throughput. However, this can introduce contention for shared resources amongst threads running concurrently in SMT mode. In order to enable the programmer to control the ratio in which resources are shared, the IBM POWER5 processor allows prioritization of one thread over another. The processor also implements Dynamic Resource Balancing (DRB) hardware, which throttles back a thread that monopolizes architectural resources by reducing its thread priority. Unlike thread priorities, the DRB is not tunable by software. In this paper, the hardware thread priorities that give best processor throughput are referred to as optimal hardware thread priorities. The research described in this paper answers the following question: Does the POWER5’s DRB influence the identification of optimal hardware thread priorities for a given pair of threads running concurrently in SMT mode, i.e., a co-schedule? To answer this question we used a POWER5 simulator and compared cycles per instruction (CPI) with DRB enabled and DRB disabled while simulating application runs for application pairs composed of SPEC CPU2000 and STREAM benchmarks. Our results show that (1) there was less than 1% difference between the CPIs of the threads of all coschedules except for co-schedules executing a SPEC floating-point intensive benchmark and a SPEC integerintensive benchmark; (2) whether DRB is enabled or disabled, approximately 40% of co-schedules do not experience best performance with equal priorities; and (3) approximately 69% of the co-schedules experienced best performance at the same priorities with DRB enabled and DRB disabled. Thus, the enabling or disabling of the POWER5’s DRB does not have a significant impact on the identification of a co-schedule’s optimal thread priorities.