Variable Instruction Fetch Rate to Reduce Control Dependent Penalties

In order to overcome the branch execution penalties of hard-to-predict instruction branches, two new instruction fetch micro-architectural methods are proposed in this paper. In addition, to compare performance of the two proposed methods, different instruction fetch policy schemes of existing multi-branch path architectures are evaluated. An improvement in Instructions Per Cycle (IPC) of 29.4% on average over single-thread execution with gshare branch predictor on SPEC 2000/2006 benchmark is shown. In this paper, wide pipeline machines are simulated for evaluation purposes. The methods discussed in this paper can be extended to High Performance Scientific Computing needs, if the demands of IPC improvement are far more critical than $cost. Keywords—IPC, Branch Prediction, Multi-branch Path Executions, cycle-accurate simulation, InstructionLevel Parallelism, SMT processors, Superscalar, confidence estimator, SPEC benchmarks, High Performance Computing.