Circuit Partitioning using High Level Design Information

2 PARTITIONING APPROACHES Partitioning digital circuits has become a key problem in the Computer Aided Engineering area during the last years. Design benefits of new technologies like MultiChip-Module designs or logic emulation strongly depends on partitioning results. Most published approaches are based on abstract graph models constructed from flat netlists, thus taking only connectivity information into consideration. The approach presented in this paper uses specific information about design modules, higher level design structures and hierarchy to create a cluster structure. Followed by a standard iterative improvement algorithm our results are comparable to best partitioning results published before and outperform them in special cases. Partitioning approaches can be classified into four different groups: Iterative improvement algorithms, also known as refinement or top-down algorithms, take a (e.g. randomly generated) startpartition and optimize the objective function by interchanging [KeLi69] or moving elements [FiMa82]. Based on Ford & Fulkersons maxflow min-cut theorem [FoFu62] some algorithms use repeated max-flow min-cut [YaWo94], single [Pla90] or multi commodity [LeRa88] flow techniques for partitioning. Recently, algorithms based on quadratic programming techniques, also referred to spectral or eigenvalue based methods, have been presented showing good partitioning results [RiDo94], [HaKa91].