Reduction of Network Cost and Wiring in Ranade's Butterfly Routing

The class of n{input butterry networks is very important for the design of scalable parallel machines because of constant node degree, depth log n and the existence of routing algorithms capable of delivering n log n packets, forming a log n{relation (log n packets destined to each output), in time O(log n) with constant length buuers. Implementations however show ugly wiring. We present a method that, in comparison to the obvious implementation, reduces the number of chips and the number of links between chips in Ranade's butterry routing by a factor of more than two. The chips remain connected as a butterry network. This reduction in space simpliies cooling, power supply and allows for shorter links thus reducing wire delay.