Performance Tradeoffs in the VLSI Implementation of the Sphere Decoding Algorithm

Sphere decoding (SD) allows to solve highdimensional MIMO maximum likelihood detection problems with significantly lower complexity than other methods. The SD algorithm has, however, mostly only been analyzed with DSP implementations in mind. We show that VLSI implementations call for new performance metrics, analyze the resulting implementation tradeoffs for the decoding of complex signal constellations, and we develop design guidelines and a generic architecture. When using the `∞-norm for the sphere constraint instead of the `-norm, significant reductions in circuit complexity and improvements in tree pruning efficiency are possible at a minimum performance penalty. As a proof of concept, a high performance ASIC implementation is presented.