Fair and Comprehensive Performance Evaluation of 14 Second Round SHA-3 ASIC Implementations

Hardware implementation quality will be considered as an important factor for evaluating the NIST SHA-3 competition candidates in the second round. The most traditional and popular hardware im­ plementation method is designing ASICs with standard cells. However, to benchmark 14 second round SHA-3 ASIC designs based on a fair and comprehensive methodology can be very challenging because of the unde­ fined application scenarios, various choices of technologies and multiple optimization goals. In this paper we describe a consistent and system­ atic approach to move a SHA-3 hardware benchmark process from FPGA prototyping to ASIC implementation, and we present our latest results for ASIC evaluation of the 14 second round SHA-3 candidates. The ef­ fort reported in this paper is complementary to the effort reported in the SHA-3 conference submission ”How can we conduct fair and consistent hardware evaluation for SHA-3 candidates?” [4].