Challenges of Electronic CAD in the Nano Scale Era

Future nano scale devices will expose different characteristics than todays silicon devices. While the exponential growth of non recurring expenses (NRE, mostly due to mask sets) can be anticipated even for new technologies, problems such as the dramatically increased defect density require new approaches to build functional devices at reasonable prices. Improved CAD algorithms can help to solve these problems, or in some cases, they can be seen as enabling technology to broaden the use of paradigms such as reconfigurable computing. In this work we discuss in which stages of design, manufacturing, and deployment new CAD algorithms are required. 1 How to make Productive use of Billions of Logic Gates Following the road of Moore’s law, the number of transistors on a chip doubles every 24 months. After being valid for more than 40 years, the end of Moore’s law has been forecast many times now. Yet, technological advances have keep the progress intact. While the technological forecast for the next 5 to 10 years still concentrates on traditional CMOS logic realized on silicon, it seems likely that other technologies will take over in this time frame. A good candidate is CMOL[SFG03][DL05], which uses carbon nano tubes together with silicon-implemented CMOS circuits. With this technology, logic elements can be built at a much higher density than possible with lithographic processes using etching to build up physical structures. In the last year, graphene films have been found as another candidate technology for future digital devices[DSMJ09]. In contrast to CMOL, no actual logic devices have been built yet, leaving the design and cost implications unclear. However, it can be speculated that the extremely small structures used here will also be susceptible to higher defect rates.