Practical statistical simulation for efficient circuit design

In wireless handset design, specifically power amplifiers (PAs), there is constant pressure to improve time-to-market while maintaining high yields. To meet these demands, designers need to evaluate current design practices and identify areas for improvement. Presently, some PA designers spend a great deal of time bench-tuning to optimize circuits. Because this is very time consuming, the main focus is obtaining the best " nominal " performance, and process variation is generally an afterthought. Frequently, new circuit topologies are implemented and minimal sample sizes are evaluated (often on a single wafer) leading to " one-wafer wonder " results. Unfortunately, as the design is run over many wafers, normal process variations take their toll degrading the initial " hero " performance and, in the extreme case, lead to unacceptable yields. These variations are often blamed on the starting material or the fabrication process but, in reality, are due to expected process variations. Including process statistics in the simulation phase can greatly reduce the occurrence of these frustrating events. To date, the implementation of statistical simulations in microwave designs (and III–V designs, specifically) has been limited, even though it is commonplace in silicon (Si) digital or analog-mixed signal design [1–6]. What are the barriers? The first is that methodology used in the Si design community is usually centered on inherently time-consuming Monte Carlo (MC) simulations [4–7]. While necessary for most Si designs, where neighboring device mismatches are critical, the additional complexity and added simulation time makes it " unfit " for III–V designs where devices are large and wafer turnround time is short (weeks compared to months). Some Si foundries provide " corner " models, but these are derived by driving figures of merit (like f T) that are not necessarily important for RF design. Most foundries provide customers with an option to fabricate " spread " wafer lots that capture the expected process variation (by changing process variables) [8], but do not provide a way to easily simulate that set of wafers to allow designers to close the loop with simulation. Another barrier is that many approaches for modeling of GaAs devices are curve-fitting-based rather than being physics-and scaling-based. Curve fitting makes it cumbersome , if not impossible; to provide a set of models that accurately tracks real-life process variations. The final impediment is that most statistical analysis training focuses on using a particular software package, separate from the circuit simulator [9]. …