An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels
نویسندگان
چکیده
In this work we present a full analog turbo decoder for hard-disk EPR-IV read channels in CMOS technology. The design is based on a current-mode approach developed by Loeliger et al. [1], for the analog implementation of sum-product algorithms. The circuits main attractions are the coding gain offered by turbo codes over the uncoded EPR-IV channel, and the relative simplicity and power efficiency of the analog approach over the digital approach. The circuit is developed in a 0.18 μm CMOS technology and operates at a 1.8 V power supply, with a total simulated power consumption (including peripheral circuitry) of about 650 mW at 400 Mb/s.
منابع مشابه
A High-Speed Analog Turbo Decoder
A new type of iterative decoders based on analog computing networks, which are used to decode powerful error-correcting schemes, such as Turbo and Low-density parity-check (LDPC) codes, outperform their digital counterparts in terms of power consumption and speed. Only few analog Turbo decoders, all of them based on CMOS subthreshold technology have been implemented till now. This paper aims to...
متن کاملA 50 MHz 70 mW & Tap Adaptive EqualizerlViterbi Sequence Detector in 1 . 2 pm CMOS
A new architecture for digital implementation of the adaptive equalizer in Class IV Partial Response Maximum Likelihood (PRML) channels employing parallelism and pipelining is described. The architecture was used in a prototype integrated circuit in a 1.2 pm CMOS technology to implement a 50 MHz adaptive equalizer and Viterbi sequence detector dissipating 70 mW from a 3.3 V supply. 1 .O Introdu...
متن کاملA Low-Power 100 MHz Analog FIR Filter for PRML Equalization
This paper presents design of a low-power 100 MHz analog FIR filter for PRML equalization used in the read channel of hard disk drives. The chip consists of 16 channels to provide 15-tap FIR filter operation. By using rotating clocks for sample/hold operation with one dummy channel, timing constraints can be relieved, which results in low-power consumption. The chip incorporates the parallel ar...
متن کاملA 13.3-Mb/s 0.35- m CMOS Analog Turbo Decoder IC With a Configurable Interleaver
Circuits and an IC implementation of a four-state, block length 16, three-metal one-poly 0.35m CMOS analog turbo decoder with a fully programmable interleaver are presented. The IC was tested at 13.3 Mb/s, has a 1.2 s latency, and consumes 185 mW on a single 3.3-V power supply, resulting in an energy consumption of 13.9 nJ per decoded bit, thus reducing the energy consumption by 70% relative to...
متن کاملA Low-Power CMOS VGA for 50Mb/s Disk Drive Read Channels
We describe an all CMOS variable gain ampliier (VGA) suitable for use in disk drive read channels. The VGA maintains a 3dB bandwidth greater than 85 MHz throughout its gain range. This ensures good phase linearity for data transfer rates of up to 50Mb/s. The VGA provides a 25dB gain variation along an ideal exponential gain to control voltage curve and 30dB of gain control if ideal exponential ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2002