Board-level multiterminal net assignment for the partial cross-bar architecture
نویسندگان
چکیده
This paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in the digital design of clos-folded field-programmable gate array (FPGA) based logic emulation systems. The approach transforms the FPGA board-level routing task into a Boolean equation. Any assignment of input variables that satisfies the equation specifies a valid routing. We use two of the fastest Boolean satisfiability (SAT) solvers: Chaff and DLMSAT to perform our experiments. Empirical results show that the method is time-efficient and applicable to large layout problem instances.
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عنوان ژورنال:
- IEEE Trans. VLSI Syst.
دوره 11 شماره
صفحات -
تاریخ انتشار 2003