Performance Enhancements in Scaled Strained SiGe pMOSFETs with HfSiOx/TiSiN Gate Stacks

This paper is made available online in accordance with publisher policies. Please scroll down to view the document itself. Please refer to the repository record for this item and our policy information available from the repository home page for further information. To see the final version of this paper please visit the publisher's website. Access to the published version may require a subscription. Publisher statement: " © 2009 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. " enhancement commonly observed in strained SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in the compressively strained SiGe devices compared with the silicon controls. The effective channel length was extracted from I-V measurements and was found to be 40% smaller in 100 nm silicon control devices than in SiGe devices having the same lithographic gate lengths, in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled device performance. These findings demonstrate that the significant on-state performance gains of strained SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation and contact modules can be optimized for SiGe.