Theory of Modulo-Scheduled Pipelines

Extensive research work has been reported on the scheduling of hardware pipelines and software pipelining independently, One interesting problem is how to extend hardware pipeline theory to handle software pipelined loops in user programs. More specifically , the problem is how to maximize the utilization of hardware resources under modulo scheduling for a given II. In this paper, we develop a nite state automaton (FSA) based framework for analyzing and improving the utilization of Modulo-Scheduled (MS) pipelines | hardware pipeline structures operating under software pipelining. The main contributions of this paper are: 1. We establish, under certain conditions, a necessary and suucient condition for achieving the upper bound (UB Init) on the number of initiations in the given pipeline (with a xed resource reservation table) (Theorem 4.1). The condition is quite powerful, yet surprisingly simple to check. 2. We demonstrate that the pipeline reconnguration method (e.g. changing the reservation table by introducing delays in the pipeline) from classical pipeline theory can be adapted to improve the utilization of hardware pipeline, and hence obtain better modulo schedules. 3. We establish that such pipeline reconnguration method can always achieve UB Init, and hence the maximum utilization of hardware pipelines (Theorem 5.1). A procedure to accomplish delay insertion has been developed and implemented. 4. Our initial experiments show that with the insertion of a small delay, often 1 cycle, upto 90% of UB Init (and maximum utilization) of the hardware pipeline can be achieved for a wide range of IIs. This is a further evidence of the usefulness of the proposed MS-pipeline theory and the delay insertion method.