Energy Efficient Architecture Using Hardware Acceleration for Software Defined Radio Components

In order to make cognitive radio systems a practical technology to be deployed in realworld scenarios, the core Software Defined Radio (SDR) systems must meet the stringent requirements of the target application, especially in terms of performance and energy consumption for mobile platform. In this paper we present a feasibility study of hardware acceleration as an energy-efficient implementation for SDR. We identified the amplifier function from the Software Communication Architecture (SCA) for hardware acceleration since it is one of the functions called most frequently and requires intensive floating-point computation. Then, we used the Virtex5 FieldProgrammable Gate Array (FPGA) to perform a comparison between compiler floating-point support and the on-chip floating-point support. By enabling the on-chip floating-point unit (FPU), we obtained as high as 2X speedup and 50% of overall energy reduction. We achieve this with an increase of the power consumption by no more than 0.68%. This demonstrates the feasibility of the proposed approach.