A Programmable-Logic Based Multiprocessor Engine for Real-Time Vision Preprocessing

It is well known that dedicated hardware has the potential to provide the fastest execution speeds but its rigidity often deters potential users. They prefer the economies of scale and flexibility which programmable systems offer. The proposed architecture uses new generations of re-programmable logic devices and modularised hardware, thereby gaining the performance advantage of hard-wired logic with the flexibility and associated economies of programmable systems. The architecture takes the form of an extensible processing hierarchy consisting of a set of tightly coupled parallel processors, each processing a portion of the image using a classic pipeline arrangement. A programmable image splitting (and reconstruction) engine feeds this array and offers the potential of further enhancing the performance of tbe engines by restructuring the pixel distribution (bit-shuffling) so as to match the requirements of the executing algorithms. The physical implementation will be based on a modularised bus system together with EPLD processing devices.