Design and Performance Analysis of a Reconfigurable Fir Filter

FIR filtering is one of the most widely used operations performed in DSP applications. In this paper, a low power reconfigurable FIR filter is designed, in which the input data are monitored and the multipliers in the filter are disabled when both the coefficients and inputs are small enough to mitigate the effect on the filter output. Generally, since the amount of computation and the corresponding power consumption of FIR filter are directly proportional to the filter order, if we can dynamically change the filter order by turning off some of the multipliers, significant power savings can be achieved with minor degradation in performance. An amplitude detector block is used to monitor the inputs of the filter. A control signal generator counts the number of inputs that have small amplitude and the multipliers are disabled only when consecutive inputs are small. The filter is designed using VHDL, simulated in Modelsim SE 5.7g and synthesized in Xilinx ISE 8.1. The results of conventional and the Reconfigurable FIR filter are compared. Key TermsReconfigurable FIR, input monitoring, filter order.