(FPGA ’09) VPR 5.0: FPGA CAD and Architecture Exploration Tools with Single-Driver Routing, Heterogeneity and Process Scaling

The VPR toolset has been widely used in FPGA architecture and CAD research, but has not evolved over the past decade along with commercial FPGAs, to include many new architectural features. This paper describes and uses a new version of the toolset that includes four significant new features: first, it supports a broad range of single-driver routing architectures, which have significantly different architectural and electrical properties from the multi-driver approach previously modelled (and which is now employed in the majority of FPGAs sold). Second, it can now model a heterogeneous selection of hard logic blocks, which could include the hard memory and multipliers that are now ubiquitous in FPGAs. Third, we provide optimized electrical models of a wide range of architectures in different process technologies, including a range of area-delay tradeoffs for each single architecture. Prior releases of VPR did not publish even one architecture file with accurate resistance and capacitance parameters. Finally, to maintain robustness and to support future development the release includes a set of regression tests to check functionality and quality of result of the output of the tools. To illustrate the use of the new features, we present a new look at the FPGA area vs. logic block LUT size question that shows that small LUT sizes, with the use of carefully optimized electrical design and single-driver architectures, have better area (relative to 4-LUTs) than previously thought. Another experiment shows that several of the previous architectural results are invariant in moving from multi-driver to single-driver routing architecture and across a range of process technologies. Finally, we illustrate the use of the new heterogeneous feature with an experiment that shows the effect of using a hard multiplier in an FPGA.