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SRC Contract 82 - 11 - 003 Transfer of Software Methodology to VLSI Design

Frederick P. Brooks, R. Gross

چکیده

This investigation was proposed as a big·h-risk one-year exploration of VLSI design methods by a group of software engjneers, to see how applicable the complexity management techniques evolved over fifteen years of software engineering would he to the analogous VLSI design complexity problems. We said we would look at the problem for a year and then report whether there was gold in these hills. Results-Quick Net 1. There is not enough gold there to interest any of our faculty investigators in personally exploring furth er; it is less promising t han our other research opportunities. So we made no application for furtb~r support·. Professor Kye Hedlund is pursuing independent work on VLSI design methodology t hat has been influenced by our research under this contract, although it had other principal stimuli. life of the SRC contract and over t he coming year, has cost SRC nothing for salaries. The contract did pay part of the cost of a computer workstation which Major Gross shar es. 3. During the contract, Professor Hedlund , one of t he investigators, received a two year IBM Young Faculty Research Award in nationwide competition. 4. Mr. Lenny Heath , a research assistant on this contract, became interested in problems in the theory of 3-D VLSI, in particular, the problem of bow many layers are required to ensure wireability. He has lowered the previous best upper hound from nine " pages" to seven for the " book embedding" problem. His paper "Embedding Planar Graphs in Seven Pages", has been accepted for the 25th Symposium on the Foundations of Computer Science and will he published in the Proceedings in October. A ten-page extended abstract is attached. Results-Discussion Dimensionality. We found software engineering (SE) complexity management techniques to be less applicable than we had expected. I think this arises from two causes. The most important is that the interface problem between two VLSI subdesigns has three (vector) dimensions, whereas software interfaces have one vector dimension, a parameter vector describing a Logical, or information. interface. The components or the interface vector are data objects, which themselves may have quite complex structure and representation. These compon~nts may pass across the interface explicitly, as in a procedure call, or implicitly, as global variables. VLSI sub-design interfaces have this same Logical dimension, with the same data objects being passed. Except where two sub-designs each also have an interface to a third which …

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