Techniques and Tools for the Verification of Systems-on-a-Chip at the Transaction Level. (Techniques et outils pour la vérification de Systèmes-sur-Puce au niveau transaction)

The work presented in this document deals with the formal verification models of Systems-on-a-Chipat the transaction level (TLM). We present the transaction level and its variants, and remind how this newlevel of abstraction is today necessary in addition to the register transfer level (RTL) to accommodate thegrowing constraints of productivity and quality, and how it integrates in the design flow.We present a new tool, called LUSSY, that allows property-checking on transactional models writtenin SystemC. Its structure is similar to the one of a compiler: A front-end, PINAPA, that reads the sourceprogram, a semantic extractor, BISE, into our intermediate formalism HPIOM, a number of optimizationsin the component BIRTH, and code generators for provers like LUSTRE and SMV.LUSSY has been designed to have as few limitation as possible regarding the way the input programis written. PINAPA uses a novel approach to extract the information from the SystemC program, andthe semantic extraction implements several TLM constructs that have not been implemented in any otherSystemC verification tool as of now. It doesn’t require any manual annotation. The tool chain is completelyautomated.LUSSY is currently able to prove properties on small platforms. Its components are reusable to buildcompositional verification tools, or static code analyzers using techniques other than model-checking thatcan scale up more efficiently.We present the theoretical principles for each step of the transformation, as well as our implementation.The results are given for small examples, and for a medium size case-study called EASY. Experimentingwith LUSSY allowed us to compare the various tools we used as provers, and to evaluate the effects of theoptimizations we implemented.ACM Classification: B.6.3, D.2.4, D.3.1, F.4.3, F.3.1