Performance of VLSI Engines for Lattice Computations

We address t he problem of designin g an d building efficient custo m Vl.Sl-besed processors to do computat ions on large multi -dimensional lat tices. The design t ra deoffs for two architectures which provid e practical engines for lattice updates are deri ved and an alyzed . We find t hat I/O constit utes t he principal bottleneck of processors des igned for lat t ice computations, and we derive upp er bounds on t hroughp ut for lattice updates based on Hong and Kung's graph-pebbling argument t ha t model s I/ O. In part icular, we show that R = O(BS1/ d ) , where R is the site update rate, B is t he main memory bandwidth, S is t he processor sto rage, and d is t he dimension of th e la ttice.