FPGA Implementation of 1D and 2D DWT Architecture using Modified Lifting Scheme

Image compression is one of the prominent topics in image processing that plays a very important role in reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT for image compression. The computational complexity of DWT imposes a major challenge for the real-time use of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for computing the approximation and detailed coefficients of DWT. The modified equations use, right shift operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one; thereby minimizing the delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and consumes less than 1W of power. The design occupies less than 1% of the LUT resources on FPGA. The architecture developed is suitable for real-time image processing on FPGA platform.