An FPGA Real-time Implementation of the Chen’s Chaotic System for Securing Chaotic Communications

In this paper, we present a new approach for real-time implementation of the Chen’s chaotic system on Field Programmable Gate Array (FPGA). The approach consists on using structural hardware description language (VHDL) with a fixed-point representation, contrary to some previous works which use somewhat non optimal VHDL code generation using automatic code generation tools. The obtained real-time chaotic signals are compared with those obtained using ModelSim and Matlab. The hardware implementation exhibits good performances of throughput and cost in term of resources used. The aim of this implementation is to use this chaotic generator in secure digital chaotic communication system.