On the Computational Synthesis of CMOS Voltage Followers

A systematic method is introduced to the computational synthesis of CMOS voltage followers (VFs). The method is divided in three steps: generation of the small-signal circuitry by selection of nullators to model the behavior of a VF, and addition of norators to form nullatornorator joined-pairs; generation of the bias circuitry by addition of ideal biases according to the properties of nullators and norators; and synthesis of the joined-pairs by MOSFETs, and of the current-biases by CMOS current mirrors. It is shown that the proposed synthesis method has the capability to generate already known and new CMOS VF topologies. key words: CAD, analog synthesis, voltage follower, nullator, norator, biasing and sizing, MOSFET