CMOS Semiconductor Manufacturing Integration on Sub-micron Gate Spacer

This paper describes the details of a novel manufacturing process integration of CMOS (Complementary Metal-Oxide-Semiconductor) transistor architecture, which is incorporated into a sub-micron logic technology on 300mm wafers. As the gate length is scaling down, the spacer design for CMOS transistor becomes increasingly important especially for high performance. Experimental manufacturing process results show that the offset spacer and width can effectively increase the on-state driving current Ion and reduce the off-state leakage current off due to the high vertical fringing electric field effect arising from the side capacitor comprising of gate/offset spacer/drain extension structure. This fringing field and, in turn, the Ion/Ioff current ratio and sub-threshold swing can be strongly enhanced by increasing the dielectric constant of the offset space. The minimum-sized features are finished not by photolithography but by the CVD (chemical vapor deposition) film thickness and plasma etching processes. Therefore, the spacer technology yields critical dimension variations of minimum-sized features that are much smaller than achieved by optimal etching process. As a result, the lateral length of the spacer structure can be well controlled and the electrical performance of the later formed semiconductor device can be well controlled as well. Therefore, the reliability of the semiconductor device is increased.