Implementation and Delay Estimation of Concurrent Error Detection Arithmetic Adders Using Hardware Redundancy Based on Dual Rail Encoding
چکیده
Arithmetic functions are the most used operations in VLSI circuits. So the design of adders with high reliability and speed operation are of major concern in such circuits. This paper presents a methodology for designing totally self-checking Arithmetic adders for VLSI circuits and FPGA implementation using Verilog HDL. It detects the presence of all single stuck-at faults on-line that may occur in digital systems. The design encodes sum/carry/propagate bits of an adder based on 2-rail codes and then encoded bits are checked by using self-checking checker. The design is proposed for carry-skip and carry look-ahead adders. The total overhead and delay varies slightly when compared to the adders without self-checking capability; thus the reliability glance can be inserted with little increased overhead & delay. The totally self-checking system (TSC) can be implemented through an Application Specific Integrated Circuit or Field Programmable Gate Array. FPGA implementation is preferable, as its design is less complex and low cost compared to ASIC design. This paper illustrates the low cost advanced self-checking scheme using Xilinx ISE 11 and Digilent Nexys2 FPGA board.