Diseño de Sistemas de Memoria Cache de Alto Rendimiento aplicando Algoritmos de Acceso Seudo-Especulativo

The gap between the cycle time of processor and the access time to memory go on being eminent. The processor performance increases about 60% by year because of reduction of cycle time and the rise in the number of instruction processed by cycle. Nevertheless, DRAM memories access time only reach an improvement about 10% by year although capacity is duplicate every one and a half year, according to Moore’s Law . To reduce this contrast of times, a hierarchical memory organization is used, with the purpose that the level near to the processor holds the content of main memory that is foreseen to be referenced. The factors that affect the performance are the necessary time to get one data to the first level L1 the cache and the fraction of references satisfied from the cache. Our work consists in increase the frequency of hits and reduces the average memory-access time in cache, without increase the cycle time of processor supported inside limit fair the access latency. Using address prediction at capacity to guide the management and access to the firs level cache, in sequential access caches, we propose a dynamic and clever scheme to access caches memories. The evaluation shows that this scheme can achieve an average improvement in the average memory-access time of 14.71% 11.47% and 12.80% in caches of 8kb, 16kb and 32kb of capability respectively, over conventional directed mapped caches memories. At the same time, our scheme maintains the frequency of miss similar to the conventional 2-way associative cache memory.