A 5.3 GHz Programmable Divider for HiPerLAN in 0.25 m CMOS

A 5.3 GHz low voltage CMOS frequency divider whose modulus can be varied from 220 to 224 is presented. Programmability is achieved by switching between different output phases of a D flip-flop (DFF). An improved glitchfree phase switching technique through the use of a retimer circuit is introduced. A high speed low voltage DFF circuit is given. The programmable divider fabricated in m technology occupies 0.09 mm and consumes 24 mA at 1.8 V and 37 mA at 2.2 V. 5.5 GHz operation with 300mVpk single ended input is achieved with a 2.2 V supply. The residual phase noise at the output is dBc/Hz at an offset of 1 kHz from the carrier.