Test Scheduling Optimization For Globally Asynchronous Locally Synchronous System-On-Chip Using Genetic Algorithm

Test Methodologies for Globally Asynchronous Locally Synchronous (GALS) System On a Chip (SOC) are a subject of growing research interest since they appear to offer benefits in low power applications and promise greater design modularity. Pre-designed cores and reusable modules are popularly used in the design of large and complex Systems. As the size and complexity of System increase, the test effort, including test development effort, test data volume, and test application time, has also significantly increased. Available techniques for testing of core-based systems on a chip do not provide a systematic means for compact test solutions. A test solution for a complex system requires good optimization of Test Scheduling and Test Access Mechanism (TAM). In this paper, we provide a Test Scheduling Optimization for Globally Asynchronous Locally Synchronous System-On-Chip Using Genetic Algorithm that gives compact test scheduling. Key-Words: Systems on a Chip (SOC), Asynchronous Circuits, Core-Based Systems, Test Scheduling, Test Access Mechanism, Reusable Modules, Very Large Scale Integration (VLSI), Genetic Algorithm.