Microgrids - The exploitation of massive on-chip concurrency

In this paper a general model for instruction-level distributed computing is described. This model provides an explicit description of instruction-level concurrency and allows for scalable implementations of various types of wide-issue multiprocessors. The model is based on microthreading, a hardware-supported multithreading paradigm that schedules small fragments of code dynamically. This model is a replacement for out-of-order issue, currently used in superscalar processors, in order to expose higher levels of concurrent instruction issue. The model describes parametric concurrency, based on loops, and produces scheduleindependent binary code. Moreover, this model can be implemented in a fully scalable manner and it is shown here that the instruction issue logic, the distributed register-files and communication structures all scale linearly with issue width. Out-of-order issue has the distinct advantage of backward compatibility in binary code execution as the concurrency is implicit but the scalability disadvantages will eventually outweigh this; in the out-of-orderissue model there is a square-law scaling in the size of issue logic with issue width and a cube law scaling of the global register-file with issue width. Microthreading does not yield concurrency unless existing code is recompiled using the concurrency controls introduced by this model. However, backward compatibility is still possible and some speedup on legacy code may be achieved by binary-code translation.