VLSI Architecture for an Efficient Memory Built in Self Test for Configurable Embedded SRAM Memory

Memories are the most dominating blocks present on a chip. All types of chips contain embedded memories such as a Read Only Memory (ROM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and flash memory. Testing of these memories is a very tedious and challenging job as area over head, testing time and cost of the test play an important role. In this work an efficient VLSI architecture for MBIST (Memory Built in Self Test) which incorporates a modified March Yalgorithm using concurrent technique and a modified Linear Feedback Shift Register (LFSR) based address generator is proposed. Because of concurrency in testing the sequences the test results were observed in less time than the traditional March tests. The synthesis and simulation of the design is done using Xilinx ISE software. The design is coded in Verilog and the experimental result when compared with similar existing works shows a reduction in complexity and delay time.